\doxysection{OPAMP\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_o_p_a_m_p___type_def}{}\label{struct_o_p_a_m_p___type_def}\index{OPAMP\_TypeDef@{OPAMP\_TypeDef}}


Operational Amplifier (OPAMP)  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_p_a_m_p___type_def_aa3123f8a6ca8605b6687b9ee3f11e8ef}{CSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_p_a_m_p___type_def_a6a80544bc693d9c51045b3652c43fd22}{OTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_p_a_m_p___type_def_ac746a0334c3a1c564e05074578280c69}{HSOTR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Operational Amplifier (OPAMP) 

\label{doc-variable-members}
\Hypertarget{struct_o_p_a_m_p___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_o_p_a_m_p___type_def_aa3123f8a6ca8605b6687b9ee3f11e8ef}\index{OPAMP\_TypeDef@{OPAMP\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!OPAMP\_TypeDef@{OPAMP\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_o_p_a_m_p___type_def_aa3123f8a6ca8605b6687b9ee3f11e8ef} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OPAMP\+\_\+\+Type\+Def\+::\+CSR}

OPAMP control/status register, Address offset\+: 0x00 \Hypertarget{struct_o_p_a_m_p___type_def_ac746a0334c3a1c564e05074578280c69}\index{OPAMP\_TypeDef@{OPAMP\_TypeDef}!HSOTR@{HSOTR}}
\index{HSOTR@{HSOTR}!OPAMP\_TypeDef@{OPAMP\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HSOTR}{HSOTR}}
{\footnotesize\ttfamily \label{struct_o_p_a_m_p___type_def_ac746a0334c3a1c564e05074578280c69} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OPAMP\+\_\+\+Type\+Def\+::\+HSOTR}

OPAMP offset trimming register for high speed mode, Address offset\+: 0x08 \Hypertarget{struct_o_p_a_m_p___type_def_a6a80544bc693d9c51045b3652c43fd22}\index{OPAMP\_TypeDef@{OPAMP\_TypeDef}!OTR@{OTR}}
\index{OTR@{OTR}!OPAMP\_TypeDef@{OPAMP\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OTR}{OTR}}
{\footnotesize\ttfamily \label{struct_o_p_a_m_p___type_def_a6a80544bc693d9c51045b3652c43fd22} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OPAMP\+\_\+\+Type\+Def\+::\+OTR}

OPAMP offset trimming register for normal mode, Address offset\+: 0x04 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
